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| DS05-11460-1E MEMORY Mobile FCRAMTM CMOS 32 M Bit (2 M ord w MB82DP02183F NOITP RCSED x16bit) -65L Mobile Phone Application Specific Memory The MB82DP02183F is a CMOS Fast Cycle Random Access Memory (FCRAM*) with asynchronous Static Random Access Memory (SRAM) interface containing 33, 554, 432 storages accessible in a 16-bit format. This MB82DP02183F is suited for mobile applications such as Cellular Handset and PDA. *: FCRAM is a trademark of Fujitsu Microelectronics Limited, Japan SETRU AF * * * * * * * Asynchronous SRAM Interface Fast Access Time : tAA = tCE = 65 ns Max 8 words Page Access Capability : tPAA = 20 ns Max Low Voltage Operating Condition : VDD = 2.6 V to 3.1 V Operating Temperature: TA = 0 C to + 70 C Byte Control by LB and UB Low Power Consumption : IDDA1 = 30 mA Max IDDS1 = 120 A Max * Various Power Down mode : Sleep 4 M-bit Partial 8 M-bit Partial SNOIT AC F EP M a r met P Access Time (Max) (tCE, tAA) Active Current (Max) (IDDA1) Standby Current (Max) (IDDS1) Power Down Current (Max) (IDDPS) M B82DP0 1 3F-65L 65 ns 30 mA 120 A 10 A Copyright(c)2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved 2009.8 MB82DP02183F-65L PIN ASSIGNMENT (TOP VIEW) A B C D E F G H J K L M 8 7 6 5 4 3 2 1 NC NC NC NC A11 A8 WE DU LB A15 A12 A19 CE2 DU UB A6 A3 NC A13 A9 A20 DU A18 A5 A2 NC A14 A10 A16 NC DQ6 NC DQ15 VSS DQ7 DQ14 DQ5 NC DQ11 DQ2 DQ8 NC NC NC NC DQ13 DQ12 DQ4 DQ3 VDD VDD DQ10 DQ0 CE1 A17 A4 A1 DQ1 VSS A0 DQ9 OE NC NC NC NC A7 NC NC NC NC (BGA-71P-M03) PIN DESCRIPTION Pin Name A20 to A0 CE1 CE2 WE OE LB UB DQ7 to DQ0 DQ15 to DQ8 VDD VSS NC DU Address Input Chip Enable 1 (Low Active) Chip Enable 2 (High Active) Write Enable (Low Active) Output Enable (Low Active) Lower Byte Control (Low Active) Upper Byte Control (Low Active) Lower Byte Data Input/Output Upper Byte Data Input/Output Power Supply Voltage Ground No Connection Don't Use Description 2 DS05-11460-1E MB82DP02183F-65L BLOCK DIAGRAM VDD VSS A20 to A0 Address Latch & Buffer Row Decoder Memory Cell Array 33,554,432 bits DQ7 to DQ0 I/O Data Buffer DQ15 to DQ8 Input Data Latch & Control Sense/Switch Output Data Control Column Decoder Address Latch & Buffer CE2 Power Control CE1 WE LB UB OE Timing Control DS05-11460-1E 3 MB82DP02183F-65L FUNCTION TRUTH TABLE Mode Standby (Deselect) Output Disable*1 Output Disable (No Read) Read (Upper Byte) H Read (Lower Byte) Read (Word) No Write Write (Upper Byte) L Write (Lower Byte) Write (Word) Power Down*2 L X X X H*4 L L X H L X Valid Valid X Input Valid Invalid H L L L L H H H L H L Valid Valid Valid Valid CE2 H CE1 H WE X H OE X H LB X X H H UB X X H L A20 to A0 X *3 Valid Valid DQ7 to DQ0 High-Z High-Z High-Z High-Z Output Valid Output Valid Invalid Invalid DQ15 to DQ8 High-Z High-Z High-Z Output Valid High-Z Output Valid Invalid Input Valid Input Valid Input Valid High-Z High-Z Note : L = VIL, H = VIH, X can be either VIL or VIH, High-Z = High impedance *1 : Should not be kept this logic condition longer than 1 s. *2 : Power Down mode can be entered from standby state and all DQ pins are in High-Z state. Data retention depends on the selection of Power Down program. Refer to " POWER DOWN" for the detail. *3 : Can be either VIL or VIH but must be valid before read or write. *4 : OE can be VIL during write operation if the following conditions are satisfied; (1) Write pulse is initiated by CE1. Refer to "(12) Read/Write Timing 1-1 (CE1 Control)" in " TIMING DIAGRAMS". (2) OE stays VIL during write cycle. 4 DS05-11460-1E MB82DP02183F-65L POWER DOWN * Power Down The Power Down is low power idle state controlled by CE2. CE2 Low drives the device in Power Down mode and maintains low power idle state as long as CE2 is kept Low. CE2 High resumes the device from Power Down mode. This device has three Power Down modes, Sleep, 4 M-bit Partial and 8 M-bit Partial. The selection of Power Down mode can be programmed by series of read/write operation. Each mode has following data retention features. Mode Data Retention Retention Address Sleep (default) 4 M-bit Partial 8 M-bit Partial No 4 M bits 8 M bits N/A 000000h to 03FFFFh 000000h to 07FFFFh The default state is Sleep and it is the lowest power consumption but all data will be lost once CE2 is brought to Low for Power Down. It is not required to program to Sleep mode after power-up. * Power Down Program Sequence The program requires total six read/write operations with unique address and data. The device should be in standby mode in the interval between each read/write operation. The following table shows the detail sequence. Cycle # Operation Address Data #1 #2 #3 #4 #5 #6 Read Write Write Write Write Read 1FFFFFh (MSB) 1FFFFFh 1FFFFFh 1FFFFFh 1FFFFFh Address Key Read Data (RDa) RDa RDa Don't Care (X) X Read Data (RDb) The Cycle#1 is to read from most significant address (MSB). The Cycle#2 and Cycle#3 are to write to MSB. If the Cycle#2 or Cycle#3 is written into the different address, the program is cancelled and the data written by the Cycle#2 or Cycle#3 is valid as a normal write operation. It is recommended to write back the data (RDa) read by Cycle#1 to MSB in order to secure the data. The Cycle#4 and Cycle#5 are to write to MSB. The data of Cycle#4 and Cycle#5 becomes the same arbitrary data (Don't-Care). If the Cycle#4 or Cycle#5 is written into different address, the program is also cancelled but write data may not be written as normal write operation. The Cycle#6 is to read from specific address key for mode selection. And read data (RDb) is invalid. Once this program sequence is performed from a Partial mode to the other Partial mode, the written data stored in memory cell array may be lost. Therefore, this program should be performed prior to regular read/write operation if Partial Power Down mode is used. * Address Key The address key has following format. Mode Sleep (default) 4 M-bit Partial 8 M-bit Partial DS05-11460-1E Address A20 1 1 0 A19 1 0 1 A18 to A0 1 1 1 Hexadecimal 1FFFFFh 17FFFFh 0FFFFFh 5 MB82DP02183F-65L ABSOLUTE MAXIMUM RATINGS Parameter Power Supply Voltage* Input Voltage* Output Voltage* Short Circuit Output Current Storage Temperature * : All voltages are referenced to VSS. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Symbol VDD VIN VOUT IOUT TSTG Rating Min - 0.5 - 0.5 - 0.5 - 50 - 55 Max + 3.6 + 3.6 + 3.6 + 50 + 125 Unit V V V mA o C RECOMMENDED OPERATING CONDITIONS Parameter Power Supply Voltage*1 Input High Voltage *1, *2 Input Low Voltage *1, *3 Ambient Temperature Symbol VDD VSS VIH VIL TA Value Min 2.6 0 VDD x 0.8 - 0.3 0 Max 3.1 0 VDD + 0.2 VDD x 0.2 + 70 Unit V V V V C *1 : All voltages are referenced to VSS. *2 : Maximum DC voltage on input or I/O pins is VDD + 0.2 V. During voltage transitions, inputs may overshoot to VDD + 1.0 V for periods of up to 5 ns. *3 : Minimum DC voltage on input or I/O pins is -0.3 V. During voltage transitions, inputs may undershoot VSS to -1.0 V for periods of up to 5 ns. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. PACKAGE PIN CAPACITANCE (f = 1 MHz, TA = +25 C) Parameter Address Input Capacitance Control Input Capacitance Data Input/Output Capacitance Symbol CIN1 CIN2 CIO Test conditions VIN = 0 V VIN = 0 V VIO = 0 V Value Min Typ Max 5 5 8 Unit pF pF pF 6 DS05-11460-1E MB82DP02183F-65L (3) Power Down Parameters (Under recommended operating conditions unless otherwise noted) Parameter CE2 Low Setup Time for Power Down Entry CE2 Low Hold Time after Power Down Entry CE1 High Hold Time following CE2 High after Power Down Exit [Sleep mode only] CE1 High Hold Time following CE2 High after Power Down Exit [not in Sleep mode] CE1 High Setup Time following CE2 High after Power Down Exit *1 : Applicable also to power-up. *2 : Applicable when Partial mode is set. (4) Other Timing Parameters (Under recommended operating conditions unless otherwise noted) Parameter CE1 High to OE Invalid Time for Standby Entry CE1 High to WE Invalid Time for Standby Entry CE2 Low Hold Time after Power-up CE1 High Hold Time following CE2 High after Power-up Input Transition Time Symbol tCHOX tCHWX tC2LH tCHH tT Value Min 10 10 50 300 1 Max 25 Unit ns ns s s ns *2 *1 Notes Symbol tCSP tC2LP tCHH tCHHP tCHS Value Min 10 65 300 65 0 Max Unit ns ns s ns ns *1 *2 *1 Notes *1 : Some data might be written into any address location if tCHWX(Min) is not satisfied. *2 : The Input Transition Time (tT) at AC testing is 5 ns as shown in below. If actual tT is longer than 5 ns, it may violate AC specification of some timing parameters. (5) AC Test Conditions Parameter Input High Voltage Input Low Voltage Input Timing Measurement Level Input Transition Time * AC Measurement Output Load Circuit VDD 0.1 F VSS Device under Test 50 pF Output Symbol VIH VIL VREF tT Test Setup Between VIL and VIH Value VDD x 0.8 VDD x 0.2 VDD x 0.5 5 Unit V V V ns 10 DS05-11460-1E MB82DP02183F-65L TIMING DIAGRAMS (1) Read Timing 1 (Basic Timing) tRC Address tASC tCE Address Valid tCHAH tASC CE1 tOE tCP tCHZ OE tOHZ tBA LB, UB tBLZ tOLZ tOH tBHZ DQ (Output) tCLZ Valid Data Output Note : This timing diagram assumes CE2 = H and WE = H. DS05-11460-1E 11 MB82DP02183F-65L (2) Read Timing 2 (OE Control & Address Access) tRC tAX tRC Address Address Valid Address Valid tAA tOHAH tAA CE1 Low tASO tOE OE LB, UB tOHZ tOLZ tOH Valid Data Output tOH Valid Data Output DQ (Output) Note : This timing diagram assumes CE2 = H and WE = H. 12 DS05-11460-1E MB82DP02183F-65L (3) Read Timing 3 (LB , UB Byte Control Access) tAX tRC tAX Address tAA Address Valid CE1, OE Low tBA tBA LB tBA UB tBHZ tBLZ tOH tBLZ tBHZ tOH DQ7 to DQ0 (Output) Valid Data Output tBLZ Valid Data Output tBHZ tOH DQ15 to DQ8 (Output) Valid Data Output Note : This timing diagram assumes CE2 = H and WE = H. DS05-11460-1E 13 MB82DP02183F-65L (4) Read Timing 4 (Page Address Access after CE1 Control Access) tRC Address (A20 to A3) tRC Address Valid tPRC Address Valid tPRC Address Valid tPRC Address Valid Address (A2 to A0) tASC Address Valid tPAA tPAA tPAA tCHAH CE1 tCE tCHZ OE LB, UB tCLZ tOH tOH tOH tOH DQ (Output) Valid Data Output (Normal Access) Note : This timing diagram assumes CE2 = H and WE = H. Valid Data Output (Page Access) 14 DS05-11460-1E MB82DP02183F-65L (5) Read Timing 5 (Random and Page Address Access) tRC tAX tRC tAX Address (A20 to A3) tRC Address Valid tPRC Address Valid Address Valid tRC Address Valid tPRC Address Valid Address (A2 to A0) Address Valid tAA tPAA tAA tPAA CE1 LOW tASO tOE OE tBA LB, UB tOLZ tOH tOH tOH tOH DQ (Output) tBLZ Valid Data Output (Normal Access) Valid Data Output (Page Access) Notes : * This timing diagram assumes CE2 = H and WE = H. * Either or both LB and UB must be Low when both CE1 and OE are Low. DS05-11460-1E 15 MB82DP02183F-65L (6) Write Timing 1 (Basic Timing) tWC Address tAS Address Valid tCW tWR tAS CE1 tCP tAS tWP tWR tAS WE tAS tWR tWHP tBW tAS LB, UB tOHCL tBHP OE tDS tDH DQ (Input) Valid Data Input Note : This timing diagram assumes CE2 = H. 16 DS05-11460-1E MB82DP02183F-65L (7) Write Timing 2 (WE Control) tWC tWC Address Address Valid Address Valid tOHAH CE1 Low tAS tWP tWR tAS tWP tWR WE tWHP LB, UB tOES OE tOHZ tDS tDH tDS tDH DQ (Input) Valid Data Input Valid Data Input Note : This timing diagram assumes CE2 = H. DS05-11460-1E 17 MB82DP02183F-65L (8) Write Timing 3-1 (WE, LB, UB Byte Write Control) tWC tWC Address Address Valid Address Valid CE1 Low tAS tWP tAS tWP WE tWR tWHP tBS tBH LB tBS tBH tWR UB tDS tDH DQ7 to DQ0 (Input) tDS tDH DQ15 to DQ8 (Input) Valid Data Input Valid Data Input Note : This timing diagram assumes CE2 = H and OE = H. 18 DS05-11460-1E MB82DP02183F-65L (9) Write Timing 3-2 (WE, LB, UB Byte Write Control) tWC tWC Address Address Valid Address Valid CE1 Low tWR tWR WE tAS tBW tWHP tBS tBH LB tBH tAS tBW tBS UB tDS tDH DQ7 to DQ0 (Input) tDS tDH DQ15 to DQ8 (Input) Valid Data Input Valid Data Input Note : This timing diagram assumes CE2 = H and OE = H. DS05-11460-1E 19 MB82DP02183F-65L (10) Write Timing 3-3 (WE, LB, UB Byte Write Control) tWC tWC Address Address Valid Address Valid CE1 Low WE tAS tBW tWR tWHP tBH tBS LB tBS tBH tAS tBW tWR UB tDS tDH DQ7 to DQ0 (Input) tDS tDH DQ15 to DQ8 (Input) Valid Data Input Valid Data Input Note : This timing diagram assumes CE2 = H and OE = H. 20 DS05-11460-1E MB82DP02183F-65L (11) Write Timing 3-4 (WE, LB, UB Byte Write Control) tWC tWC Address Address Valid Address Valid CE1 Low WE tAS tBW tWR tBHP tDS tDH tDS tDH tAS tBW tWR LB DQ7 to DQ0 (Input) tAS Valid Data Input tBW tWR tAS tBW Valid Data Input tWR UB tDS tDH tBHP tDS tDH DQ15 to DQ8 (Input) Valid Data Input Valid Data Input Note : This timing diagram assumes CE2 = H and OE = H. DS05-11460-1E 21 MB82DP02183F-65L (12) Read / Write Timing 1-1 (CE1 Control) tWC tRC Address tCHAH tAS Write Address tWR tCW tASC Read Address tCHAH tCE CE1 tCP tCP WE UB, LB tOHCL OE tCHZ tOH tDS tDH tCLZ tOH DQ Read Data Output Write Data Input Read Data Output Notes : * This timing diagram assumes CE2 = H. * Write address is valid from either CE1 or WE of last falling edge. 22 DS05-11460-1E MB82DP02183F-65L (13) Read / Write Timing 1-2 (CE1, WE, OE Control) tWC tRC Address tCHAH tAS Write Address tWR tASC Read Address tCHAH tCE CE1 tCP tWP tCP WE UB, LB tOHCL tOE OE tCHZ tOH tDS tDH tOLZ tOH DQ Read Data Output Write Data Input Read Data Output Notes : * This timing diagram assumes CE2 = H. * OE can be fixed Low during write operation if it is CE1 controlled write at Read-Write-Read sequence. DS05-11460-1E 23 MB82DP02183F-65L (15) Read / Write Timing 3 (OE, WE, LB, UB Control) tWC tRC Address Write Address Read Address tAA tOHAH tOHAH CE1 Low WE tOES tAS tBW tWR tBA UB, LB tBHZ tASO OE tOH tDS tDH tWHOL tBHZ tBLZ tOH DQ Read Data Output Write Data Input Read Data Output Notes : * This timing diagram assumes CE2 = H. * CE1 can be tied to Low for WE and OE controlled operation. * Read data will be available after tAA from WE = H if read address are not changed from write address. (16) Power-up Timing 1 CE1 tCHS tC2LH CE2 tCHH VDD 0V VDD (Min) Note : The tC2LH specifies after VDD reaches specified minimum level. DS05-11460-1E 25 MB82DP02183F-65L (19) Standby Entry Timing after Read or Write CE1 tCHOX tCHWX OE WE Active (Read) Standby Active (Write) Standby Note : Both tCHOX and tCHWX define the earliest entry timing for standby mode. DS05-11460-1E 27 MB82DP02183F-65L (20) Power Down Program Timing tRC tWC MSB*1 tWC MSB*1 tWC MSB*1 tWC MSB*1 tRC Address MSB*1 Key*2 tCP*3 tCP tCP tCP tCP tCP CE1 OE WE LB, UB*4 DQ RDa RDa RDa X X RDb Cycle #1 Cycle #2 Cycle #3 Cycle #4 Cycle #5 Cycle #6 *1 : The all address inputs must be High from Cycle #1 to #5. *2 : The address key must conform to the format specified in " POWER DOWN". If not, the operation and data are not guaranteed. *3 : After tCP following Cycle #6, the Power Down program is completed and returned to the normal operation. *4 : Byte read or write is available in addition to word read or write. At least one byte control signal (LB or UB) needs to be Low. 28 DS05-11460-1E MB82DP02183F-65L FUJITSU MICROELECTRONICS LIMITED Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0722, Japan Tel: +81-3-5322-3329 http://jp.fujitsu.com/fml/en/ For further information please contact: North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://www.fma.fujitsu.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/microelectronics/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 206 Kosmo Tower Building, 1002 Daechi-Dong, Gangnam-Gu, Seoul 135-280, Republic of Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. 151 Lorong Chuan, #05-08 New Tech Park 556741 Singapore Tel : +65-6281-0770 Fax : +65-6281-0220 http://www.fmal.fujitsu.com/ FUJITSU MICROELECTRONICS SHANGHAI CO., LTD. Rm. 3102, Bund Center, No.222 Yan An Road (E), Shanghai 200002, China Tel : +86-21-6146-3688 Fax : +86-21-6335-1605 http://cn.fujitsu.com/fmc/ FUJITSU MICROELECTRONICS PACIFIC ASIA LTD. 10/F., World Commerce Centre, 11 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel : +852-2377-0226 Fax : +852-2376-3269 http://cn.fujitsu.com/fmc/en/ Specifications are subject to change without notice. For further information please contact each office. All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited: Sales Promotion Department |
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